Mobile electronic devices, such as digital cameras, portable digital assistants, portable audio/video players and mobile terminals continue to require mass storage memory, preferably non-volatile memory with ever increasing capacities and speed capabilities. For example, presently available audio players can have between 256 Mbytes to 40 Gigabytes of memory for storing audio/video data. Non-volatile memory such as Flash memory and hard-disk drives are preferred since data is retained in the absence of power.
Presently, hard disk drives having high densities can store 40 to 500 Gigabytes of data, but are relatively bulky. However, Flash memory, also known as solid-state drive, is popular because of their high density, non-volatility, and small size relative to hard disk drives. Flash memory technology is based on EPROM and EEPROM technologies. The term “flash” was chosen because a large number of memory cells could be erased at one time as distinguished from EEPROMs, where each byte was erased individually. Those of skill in the art will understand that Flash memory can be configured as NOR, NAND or other Flash, with NAND Flash having higher density per given area due to its more compact memory array structure. For the purpose of further discussion, references to Flash memory should be understood as being any type Flash memory.
The cell array structure of NAND flash memory consists of n erasable blocks. Each block is subdivided into m programmable pages illustrates the cell array structure of an example NAND flash memory which consists of n erasable blocks. In this example, n=2048. Each block is subdivided into m programmable pages as shown in FIGS. 1 to 3, where m=64.
Each page consists of (j+k) bytes (x8b) as shown in FIG. 3. In this example, j=2048 and k=64. The pages are further divided into a j-byte data storage region (data field) with a separate k-byte area (spare field). The k-byte area is typically used for error management functions.                1 page=(j+k) bytes.        1 block=m pages=(j+K) bytes*m.        Total memory array size=n blocks=(j+K) bytes*m*n.        
In conventional NAND flash devices, read and program operations are executed on a page basis while erase operations are executed on a block basis. All operations are driven by commands (refer to Samsung's 2Gb NAND Flash Specification: ds_k9f2gxxu0m_rev10 incorporated herein in its entirety).
The internal memory array is accessed on a page basis. The read operation starts after writing READ command followed by addresses via common I/O pins (I/O0 to I/O 7) to the device. The 2,112 bytes of data within the selected page are sensed and transferred to the page register in less than tR (data transfer time from flash array to page register) shown in FIG. 4. Once the 2,112 bytes of data are sensed and transferred from the selected page in the cell array to the data register, the data in the data register can be sequentially read from the device at, for example, 8 bits or 16 bits per cycle.
The conventional memory array is programmed on a page basis. For program operations, PROGRAM command followed by addresses and input data of 2,112 bytes is issued to the device through common I/O pins (I/O0 to I/O7). The 2,112 bytes of data are transferred to the data register during input data loading cycles and finally programmed to the selected page of the cell array less than tPROG (page program time) as shown in FIG. 5.
The memory array is erased on a block basis. For block erase operations, BLOCK ERASE command followed by block addresses is issued to the device through common I/O pins (I/O0 to I/O7). The 128K bytes of data are erased less than tBERS (block erase time) as shown in FIG. 6. Refer to NAND Flash specifications (Samsung's 2Gb NAND: ds_k9f2gxxu0m_rev10) for detailed device operations.
A NAND cell string typically consists of one string selector transistor 71, i memory cells 72 and one ground select transistor 73 which are serially connected as shown FIG. 7. The number (i) of cells per string can be varied by process technology, for example 8 cells per string or 16 cells per string or 32 cells per string. 32 memory cells per string are common in present 90 nm and 70 nm technologies. Hereinafter, ‘32’ is used for i as shown in FIG. 7.
Memory cell gates correspond to wordline 0 to 31 (W/L0 to W/L 31). The gate of string select transistor is connected to a string select line (SSL) while the drain of string select transistor is connected to bitline (B/L). The gate of ground select transistor is connected to a ground select line (GSL) while the source of ground select transistor is connected to common source line (CSL). Each wordline corresponds to a page and each string corresponds to a block.
FIGS. 8 and 9 depict physical structure of a block with 32 cells per NAND cell string. As shown in FIG. 8, there are (j+k)*8 NAND strings in a block. Thus the unit block has total (j+k)*8*32 cells. Each wordline is defined as unit page. FIG. 9 shows n blocks
Typically, flash memory cells are programmed and erased by either Fowler-Nordheim (F-N) tunneling or hot electron injection. In NAND flash memory, both erase and program are governed by F-N tunneling. The following erase and program operations are based on NAND flash memory.
During an erase operation, the top poly (i.e. top gate) of the cell is biased to Vss (ground) while the substrate of the cell is biased to erase voltage Vers (eg. approximately 20 v, source and drain are automatically biased to Vers due to junction-forward-bias from P-substrate to n+ source/drain). By this erase bias condition, trapped electrons (charge) in the floating poly (i.e. floating gate) are emitted to the substrate through the tunnel oxide as shown in FIG. 10A. The cell Vth of the erased cell is negative value as shown in FIG. 10B. In other words, the erased cell is on-transistor (normally turn-on with gate bias Vg of 0V).
During a program operation, on the contrary, the top poly (i.e. top gate) of the cell is biased to program voltage Vpgm (eg. approximately 18 v) while the substrate, source and drain of the cell are biased to Vss (ground). By this program bias condition, electrons (charge) in the substrate are injected to the floating poly (i.e. floating gate) through the tunnel oxide as shown in FIG. 11A. The cell Vth of the programmed cell is positive value as shown in FIG. 11B. In other words, the programmed cell is off-transistor (normally turn-off with gate bias Vg of 0V).
Therefore NAND flash is erased and programmed by a bi-directional (i.e. symmetrical) F-N tunneling mechanism.
One known erase scheme is illustrated in FIGS. 12 and 13. FIG. 12 shows bias condition during erase operations. The p-well substrate is biased to erase voltage Vers while bitlines and the common source line (CSL) in the selected block are clamped to Vers-0.6v through the S/D diodes of the SSL and GSL transistors. At the same time all wordlines in the selected block are biased to 0V while the string select line (SSL) and the ground select line (GSL) are biased to erase voltage Vers. Therefore entire cells in the selected block are erased by F-N tunneling as described above.
Because of block basis erase operations, erasure of memory cells in unselected blocks having the same p-well substrate must be prevented (i.e. erase inhibit). FIG. 13 shows an erase inhibit scheme to unselected blocks:                All wordlines in the selected block are biased to 0V.        All wordlines in unselected blocks are biased to Vers to compensate electrical field by Vers from the substrate.        
Table 1 shows bias conditions for the selected block and unselected blocks with the prior art 1 during erase operations.
TABLE 1Bias Conditions during Erase - Prior Art 1SELECTED BLOCKUNSELECTED BLOCKBITLINES (B/L)CLAMPED TOCLAMPED TOVers-0.6 VVers-0.6 VSTRING SELECTVersVersLINE (SSL)WORDLINES0 VVers(W/L0~W/L31)GROUND SELECTVersVersLINE (GSL)COMMON SOURCECLAMPED TOCLAMPED TOLINE (CSL)Vers-0.6 VVers-0.6 VSUBSTRATEVersVers(POCKET P-WELL)
With this erase inhibit scheme, it takes a very long total erase time to charge all wordlines in unselected blocks to erase voltage Vers. At the same time, the power consumption is very high due to charging and discharging entire wordlines in unselected blocks. Moreover, as the memory density increases, the erase time becomes much longer and the power consumption during erase operations is much higher.
In order to resolve problems in the above approach, the self-boosting erase inhibit scheme (U.S. Pat. No. 5,473,563) has been proposed and it is widely used in NAND flash memories.
For the selected block, the erase bias conditions are substantially the same as above except the SSL and GSL are floating instead of biased to Vers, as shown in FIG. 14.
To prevent erasure of memory cells in unselected blocks, all wordlines in unselected blocks are floated during erase operations as shown in FIG. 15. Therefore floated wordlines in unselected blocks are boosted to nearly erase voltage Vers by capacitive coupling between the substrate and wordlines in unselected blocks as applying erase voltage Vers to the substrate. (Floated wordlines are boosted to about 90% of Vers when the substrate of the cell array goes to Vers; however, boosted voltage level on floated wordlines is determined by coupling ratio between the substrate and wordlines.) The boosted voltage on wordlines in unselected blocks reduces electric field between the substrate and wordlines; as a result, erasure of memory cells in unselected blocks is prevented.                All wordlines in the selected block are biased to 0V.        All wordlines in unselected blocks are floating.        
Table 2 shows bias conditions during erase with this approach. There is no need to apply erase voltage Vers to wordlines in unselected blocks, which reduces power consumption during erase and reduces the erase time, because entire wordlines in unselected blocks are not needed to be biased to Vers.
TABLE 2Bias Conditions during Erase - Prior Art 2SELECTED BLOCKUNSELECTED BLOCKBITLINES (B/L)CLAMPED TOCLAMPED TOVers-0.6 VVers-0.6 VSTRING SELECTBOOSTED TOBOOSTED TOLINE (SSL)APPROX.APPROX.90% OF Vers90% OF VersWORDLINES0 VBOOSTED TO(W/L0~W/L31)APPROX.90% OF VersGROUND SELECTBOOSTED TOBOOSTED TOLINE (GSL)APPROX.APPROX.90% OF Vers90% OF VersCOMMON SOURCECLAMPED TOCLAMPED TOLINE (CSL)Vers-0.6 VVers-0.6 VSUBSTRATEVersVers(POCKET P-WELL)
Because the substrate of cells is biased to erase voltage Vers and source/drain/substrate of cells in the selected block are electrically connected, the erase operation must occur on a block basis. In other words, the minimum erasable array size is a block.
The above described Flash memories suffer from three limitations. First, bits can be programmed only after erasing a target memory array. Second, each cell can only sustain a limited number of erasures, after which it can no longer reliably store data. In other words, there is a limitation in the number of erase and program cycles to cells (i.e. Endurance, typically 10,000˜100,000 cycles). Third, the minimum erasable array size is much bigger than the minimum programmable array size. Due to these limitations, sophisticated data structures and algorithms are required to effectively use flash memories. (See for example, U.S. Pat. Nos. 5,937,425, 6,732,221 and 6,594,183.
Erase of memory cells on a page basis has been suggested in U.S. Pat. No. 5,995,417 and in patent application US 2006/0050594.